;------------------------------------------------------------------------
;                                                                       |
;   FILE        :sfr_r82d.inc                                           |
;   DATE        :Tue, Jun 03, 2014                                      |
;   DESCRIPTION :define the sfr register. (for Assembler language)      |
;   CPU GROUP   :2D                                                     |
;                                                                       |
;   This file is generated by Renesas Project Generator (Ver.4.19).     |
;   NOTE:THIS IS A TYPICAL EXAMPLE.                                     |
;------------------------------------------------------------------------
;/***********************************************************************
;*
;* Device       : R8C/2C,2D
;*
;* File Name    : sfr_r82d.inc
;*
;* Abstract     : Define the sfr register.
;*
;* History      : 1.20 (07-06-11)
;*              : 1.10 (06-12-27)
;*              : 1.00 (06-10-03)
;*
;* NOTE         : THIS IS A TYPICAL EXAMPLE.
;*
;* Copyright (C) 2006 (2007) Renesas Electronics Corporation.
;* and Renesas Solutions Corp.
;*
;************************************************************************/
;
;-------------------------------------------------------
;   Processor mode register0
;-------------------------------------------------------
pm0				.equ		0004h
pm03			.btequ		3,pm0		; Software reset bit
;
;-------------------------------------------------------
;   Processor mode register1
;-------------------------------------------------------
pm1				.equ		0005h
pm12			.btequ		2,pm1		; WDT interrupt/reset switch bit
;
;-------------------------------------------------------
;   System clock control register0
;-------------------------------------------------------
cm0				.equ		0006h
cm02			.btequ		2,cm0		; WAIT peripheral function clock stop bit
cm03			.btequ		3,cm0		; XCIN-XCOUT drive capacity select bit
cm04			.btequ		4,cm0		; Port XC Switch bit
cm05			.btequ		5,cm0		; Xin clock (Xin-Xout) stop bit
cm06			.btequ		6,cm0		; System clock division select bit0
cm07			.btequ		7,cm0		; CPU Clock Select bit
;
;-------------------------------------------------------
;   System clock control register1
;-------------------------------------------------------
cm1				.equ		0007h
cm10			.btequ		0,cm1		; All clock stop control bit
cm11			.btequ		1,cm1		; XIN-XOUT internal resistor select bit
cm12			.btequ		2,cm1		; XCIN-XCOUT internal resistor select bit
cm13			.btequ		3,cm1		; Port Xin-Xout switch bit
cm14			.btequ		4,cm1		; Low-speed on-chip oscillation stop bit
cm15			.btequ		5,cm1		; Xin-Xout drive capacity select bit
cm16			.btequ		6,cm1		; System clock division select bit1
cm17			.btequ		7,cm1		; System clock division select bit1
;
;-------------------------------------------------------
;   Module standby control register
;-------------------------------------------------------
mstcr			.equ		0008h
mstiic			.btequ		3,mstcr		; I2C Bus stanby bit 
msttrd			.btequ		4,mstcr		; Timer RD stanby bit
msttrc			.btequ		5,mstcr		; Timer RC stanby bit
;
;-------------------------------------------------------
;   Protect register
;-------------------------------------------------------
prcr			.equ		000ah
prc0			.btequ		0,prcr		; Protect bit0
prc1			.btequ		1,prcr		; Protect bit1
prc2			.btequ		2,prcr		; Protect bit2
prc3			.btequ		3,prcr		; Protect bit3
;
;-------------------------------------------------------
;   Oscillation stop detection register
;-------------------------------------------------------
ocd				.equ		000ch
ocd0			.btequ		0,ocd		; Oscillation stop detection enable bit
ocd1			.btequ		1,ocd		; Oscillation stop detection interrupt enable bit
ocd2			.btequ		2,ocd		; System clock select bit
ocd3			.btequ		3,ocd		; Clock monitor bit
;
;-------------------------------------------------------
;   Watchdog timer
;-------------------------------------------------------
wdtr			.equ		000dh		; Watchdog timer reset register
;
wdts			.equ		000eh		; Watchdog timer start register
;
wdc				.equ		000fh		; Watchdog timer control register
;
wdc7			.btequ		7,wdc		; Prescaler select bit
;
;-------------------------------------------------------
;   Address match interrupt enable register
;-------------------------------------------------------
aier			.equ		0013h
aier0			.btequ		0,aier		; Address match interrupt 0 enable bit
aier1			.btequ		1,aier		; Address match interrupt 1 enable bit
;
;-------------------------------------------------------
;   Count source protection mode register
;-------------------------------------------------------
cspr			.equ		001ch
cspro			.btequ		7,cspr		; Count source protection mode select bit
;
;-------------------------------------------------------
;   High-speed on-chip oscillator control register 0
;-------------------------------------------------------
fra0			.equ		0023h
fra00			.btequ		0,fra0		; High-speed on-chip oscillator enable bit
fra01			.btequ		1,fra0		; High-speed on-chip oscillator select bit
;
;-------------------------------------------------------
;   High-speed on-chip oscillator control register 1
;-------------------------------------------------------
fra1			.equ		0024h
;
;-------------------------------------------------------
;   High-speed on-chip oscillator control register 2
;-------------------------------------------------------
fra2			.equ		0025h
fra20			.btequ		0,fra2		; High-speed on-chip oscillator frequency switching bit
fra21			.btequ		1,fra2		; High-speed on-chip oscillator frequency switching bit
fra22			.btequ		2,fra2		; High-speed on-chip oscillator frequency switching bit
;
;-------------------------------------------------------
;   Clock prescaler reset flag
;-------------------------------------------------------
cpsrf			.equ		0028h
cpsr			.btequ		7,cpsrf		; Clock prescaler reset flag
;
;-------------------------------------------------------
;   Voltage detection register 1
;-------------------------------------------------------
vca1			.equ		0031h
vca13			.btequ		3,vca1		; Voltage detection 2 signal monitor flag
;
;-------------------------------------------------------
;   Voltage detection register 2
;-------------------------------------------------------
vca2			.equ		0032h
vca20			.btequ		0,vca2		; Internal power low consumption enable bit
vca25			.btequ		5,vca2		; Voltage detection 0 enable bit
vca26			.btequ		6,vca2		; Voltage detection 1 enable bit
vca27			.btequ		7,vca2		; Voltage detection 2 enable bit
;
;-------------------------------------------------------
;   Voltage monitor 1 circuit control register
;-------------------------------------------------------
vw1c			.equ		0036h
vw1c0			.btequ		0,vw1c		; Voltage monitor 1 interrupt / reset enable bit
vw1c1			.btequ		1,vw1c		; Voltage monitor 1 digital filter disable mode select bit
vw1c2			.btequ		2,vw1c		; Voltage change detection flag
vw1c3			.btequ		3,vw1c		; Voltage detection 1 signal monitor flag
vw1f0			.btequ		4,vw1c		; Sampling clock select bit
vw1f1			.btequ		5,vw1c		; Sampling clock select bit
vw1c6			.btequ		6,vw1c		; Voltage monitor 1 circuit mode select bit
vw1c7			.btequ		7,vw1c		; Voltage monitor 1 interrupt / reset generation condition select bit
;
;-------------------------------------------------------
;   Voltage monitor 2 circuit control register
;-------------------------------------------------------
vw2c			.equ		0037h
vw2c0			.btequ		0,vw2c		; Voltage monitor 2 interrupt / reset enable bit
vw2c1			.btequ		1,vw2c		; Voltage monitor 2 digital filter disabled mode select bit
vw2c2			.btequ		2,vw2c		; Voltage change detection flag
vw2c3			.btequ		3,vw2c		; WDT Detection Flag
vw2f0			.btequ		4,vw2c		; Sampling clock select bit
vw2f1			.btequ		5,vw2c		; Sampling clock select bit
vw2c6			.btequ		6,vw2c		; Voltage monitor 2 circuit mode select bit
vw2c7			.btequ		7,vw2c		; Voltage monitor 2 interrupt / reset generation condition select bit
;
;-------------------------------------------------------
;   Voltage monitor 0 circuit control register
;-------------------------------------------------------
vw0c			.equ		0038h
vw0c0			.btequ		0,vw0c		; Voltage monitor 0 reset enable bit
vw0c1			.btequ		1,vw0c		; Voltage monitor 0 digital filter disabled mode select bit
vw0c2			.btequ		2,vw0c		; 
vw0f0			.btequ		4,vw0c		; Sampling clock select bit
vw0f1			.btequ		5,vw0c		; Sampling clock select bit
vw0c6			.btequ		6,vw0c		; Voltage monitor 0 circuit mode select bit
vw0c7			.btequ		7,vw0c		; Voltage monitor 0 reset generation condition select bit
;
;-------------------------------------------------------
;   UART0 bit rate register
;-------------------------------------------------------
u0brg			.equ		00a1h
;
;-------------------------------------------------------
;   UART1 bit rate register
;-------------------------------------------------------
u1brg			.equ		00a9h
;
;-------------------------------------------------------
;   UART2 bit rate register
;-------------------------------------------------------
u2brg			.equ		0161h
;
;-------------------------------------------------------
;   SS control register H
;-------------------------------------------------------
sscrh			.equ		00b8h
cks0_sscrh		.btequ		0,sscrh		; Transfer clock rate select bit
cks1_sscrh		.btequ		1,sscrh		; Transfer clock rate select bit
cks2_sscrh		.btequ		2,sscrh		; Transfer clock rate select bit
mss_sscrh		.btequ		5,sscrh		; Master/Slave device select bit
rsstp_sscrh		.btequ		6,sscrh		; Receive single stop bit
;
;-------------------------------------------------------
;   IIC bus control register 1
;-------------------------------------------------------
iccr1			.equ		00b8h
cks0_iccr1		.btequ		0,iccr1		; Transmit clock select bit 3 to 0
cks1_iccr1		.btequ		1,iccr1		; Transmit clock select bit 3 to 0
cks2_iccr1		.btequ		2,iccr1		; Transmit clock select bit 3 to 0
cks3_iccr1		.btequ		3,iccr1		; Transmit clock select bit 3 to 0
trs_iccr1		.btequ		4,iccr1		; Transfer/receive select bit
mst_iccr1		.btequ		5,iccr1		; Master/slave select bit
rcvd_iccr1		.btequ		6,iccr1		; Receive disable bit
ice_iccr1		.btequ		7,iccr1		; IIC bus interface enable bit
;
;-------------------------------------------------------
;   SS control register L
;-------------------------------------------------------
sscrl			.equ		00b9h
sres_sscrl		.btequ		1,sscrl		; Clock synchronous serial I/O with chip select control part reset bit
solp_sscrl		.btequ		4,sscrl		; SOL write protect bit
sol_sscrl		.btequ		5,sscrl		; Serial data output value setting bit
;
;-------------------------------------------------------
;   IIC bus control register 2
;-------------------------------------------------------
iccr2			.equ		00b9h
iicrst_iccr2	.btequ		1,iccr2		; IIC control part reset bit
sclo_iccr2		.btequ		3,iccr2		; SCL monitor flag
sdaop_iccr2		.btequ		4,iccr2		; SDAO write protect bit
sdao_iccr2		.btequ		5,iccr2		; SDA output value control bit
scp_iccr2		.btequ		6,iccr2		; Start/Stop condition generation disable bit
bbsy_iccr2		.btequ		7,iccr2		; Bus busy bit
;
;-------------------------------------------------------
;   SS mode register
;-------------------------------------------------------
ssmr			.equ		00bah
bc0_ssmr		.btequ		0,ssmr		; Bit counter 2 to 
bc1_ssmr		.btequ		1,ssmr		; Bit counter 2 to 
bc2_ssmr		.btequ		2,ssmr		; Bit counter 2 to 
cphs_ssmr		.btequ		5,ssmr		; SSCK clock phase select bit
cpos_ssmr		.btequ		6,ssmr		; SSCK clock polarity select bit
mls_ssmr		.btequ		7,ssmr		; MSB first/ LSB first select bit
;
;-------------------------------------------------------
;   IIC bus mode register
;-------------------------------------------------------
icmr			.equ		00bah
bc0_icmr		.btequ		0,icmr		; Bit counter 2 to 0
bc1_icmr		.btequ		1,icmr		; Bit Counter 2 to 0
bc2_icmr		.btequ		2,icmr		; Bit Counter 2 to 0
bcwp_icmr		.btequ		3,icmr		; BC write protect bit
wait_icmr		.btequ		6,icmr		; Wait insertion bit
mls_icmr		.btequ		7,icmr		; MSB-First/LSB-First select
;
;-------------------------------------------------------
;   SS enable register 
;-------------------------------------------------------
sser			.equ		00bbh
ceie_sser		.btequ		0,sser		; Conflict error interrupt enable bit
re_sser			.btequ		3,sser		; Receive enable bit
te_sser			.btequ		4,sser		; Transmit enable bit
rie_sser		.btequ		5,sser		; Receive interrupt enable bit
teie_sser		.btequ		6,sser		; Transmit end interrupt enable bit
tie_sser		.btequ		7,sser		; Transmit interrupt enable bit
;
;-------------------------------------------------------
;   IIC bus interrupt enable register
;-------------------------------------------------------
icier			.equ		00bbh
ackbt_icier		.btequ		0,icier		; Transmit acknow ledge select bit
ackbr_icier		.btequ		1,icier		; Receive acknow ledge bit
acke_icier		.btequ		2,icier		; Acknowledge bit judgement select bit
stie_icier		.btequ		3,icier		; Stop condition detection interrupt enable bit
nakie_icier		.btequ		4,icier		; NACK receive interrupt enable bit
rie_icier		.btequ		5,icier		; Receive interrupt enable bit
teie_icier		.btequ		6,icier		; Transmit end interrupt enable bit
tie_icier		.btequ		7,icier		; Transmit interrupt enable bit
;
;-------------------------------------------------------
;   SS status register
;-------------------------------------------------------
sssr			.equ		00bch
ce_sssr			.btequ		0,sssr		; Conflict error flag
orer_sssr		.btequ		2,sssr		; Overrun error flag
rdrf_sssr		.btequ		5,sssr		; Receive data register full
tend_sssr		.btequ		6,sssr		; Transmit end
tdre_sssr		.btequ		7,sssr		; Transmit data empty
;
;-------------------------------------------------------
;   IIC bus status register
;-------------------------------------------------------
icsr			.equ		00bch
adz_icsr		.btequ		0,icsr		; General call address recognition flag
aas_icsr		.btequ		1,icsr		; Slave address recognition flag
al_icsr			.btequ		2,icsr		; Arbitration lost flag / Overrun error flag
stop_icsr		.btequ		3,icsr		; Stop condition detection flag
nackf_icsr		.btequ		4,icsr		; No acknow ledge detection flag
rdrf_icsr		.btequ		5,icsr		; Receive data register full
tend_icsr		.btequ		6,icsr		; Transmit end
tdre_icsr		.btequ		7,icsr		; Transmit data empty
;
;-------------------------------------------------------
;   SS mode register 2
;-------------------------------------------------------
ssmr2			.equ		00bdh
ssums_ssmr2		.btequ		0,ssmr2		; Clock synchronous serial I/O with chip select mode select bit
csos_ssmr2		.btequ		1,ssmr2		; SCS pin open drain output select bit
soos_ssmr2		.btequ		2,ssmr2		; SSO pin open drain output select bit
sckos_ssmr2		.btequ		3,ssmr2		; SSCK pin open drain output select bit
css0_ssmr2		.btequ		4,ssmr2		; SCS pin selsct bit
css1_ssmr2		.btequ		5,ssmr2		; SCS pin select bit
scks_ssmr2		.btequ		6,ssmr2		; SSCK pin select bit
bide_ssmr2		.btequ		7,ssmr2		; Bidirectional mode enable bit
;
;-------------------------------------------------------
;   Slave address register
;-------------------------------------------------------
sar				.equ		00bdh
fs_sar			.btequ		0,sar		; Format select bit
sva0_sar		.btequ		1,sar		; Slave address 6 to 0
sva1_sar		.btequ		2,sar		; Slave address 6 to 0
sva2_sar		.btequ		3,sar		; Slave address 6 to 0
sva3_sar		.btequ		4,sar		; Slave address 6 to 0
sva4_sar		.btequ		5,sar		; Slave address 6 to 0
sva5_sar		.btequ		6,sar		; Slave address 6 to 0
sva6_sar		.btequ		7,sar		; Slave address 6 to 0
;
;-------------------------------------------------------
;   SS transmit data register
;-------------------------------------------------------
sstdr			.equ		00beh
;
;-------------------------------------------------------
;   IIC bus transmit data register
;-------------------------------------------------------
icdrt			.equ		00beh
;
;-------------------------------------------------------
;   SS receive data register
;-------------------------------------------------------
ssrdr			.equ		00bfh
;
;-------------------------------------------------------
;   IIC bus receive data register
;-------------------------------------------------------
icdrr			.equ		00bfh
;
;-------------------------------------------------------
;   D-A register 0
;-------------------------------------------------------
da0				.equ		00d8h
;
;-------------------------------------------------------
;   D-A register 1
;-------------------------------------------------------
da1				.equ		00dah
;
;-------------------------------------------------------
;   D-A control register
;-------------------------------------------------------
dacon			.equ		00dch
da0e_dacon		.btequ		0,dacon		; D/A 0 output enable bit
da1e_dacon		.btequ		1,dacon		; D/A 1 output enable bit
;
;-------------------------------------------------------
;   Port
;-------------------------------------------------------
p0				.equ		00e0h
p0_0			.btequ		0,p0		; Port P00 bit
p0_1			.btequ		1,p0		; Port P01 bit
p0_2			.btequ		2,p0		; Port P02 bit
p0_3			.btequ		3,p0		; Port P03 bit
p0_4			.btequ		4,p0		; Port P04 bit
p0_5			.btequ		5,p0		; Port P05 bit
p0_6			.btequ		6,p0		; Port P06 bit
p0_7			.btequ		7,p0		; Port P07 bit
;
pd0				.equ		00e2h
pd0_0			.btequ		0,pd0		; Port P00 direction bit
pd0_1			.btequ		1,pd0		; Port P01 direction bit
pd0_2			.btequ		2,pd0		; Port P02 direction bit
pd0_3			.btequ		3,pd0		; Port P03 direction bit
pd0_4			.btequ		4,pd0		; Port P04 direction bit
pd0_5			.btequ		5,pd0		; Port P05 direction bit
pd0_6			.btequ		6,pd0		; Port P06 direction bit
pd0_7			.btequ		7,pd0		; Port P07 direction bit
;
p1				.equ		00e1h
p1_0			.btequ		0,p1		; Port P10 bit
p1_1			.btequ		1,p1		; Port P11 bit
p1_2			.btequ		2,p1		; Port P12 bit
p1_3			.btequ		3,p1		; Port P13 bit
p1_4			.btequ		4,p1		; Port P14 bit
p1_5			.btequ		5,p1		; Port P15 bit
p1_6			.btequ		6,p1		; Port P16 bit
p1_7			.btequ		7,p1		; Port P17 bit
;
pd1				.equ		00e3h
pd1_0			.btequ		0,pd1		; Port P10 direction bit
pd1_1			.btequ		1,pd1		; Port P11 direction bit
pd1_2			.btequ		2,pd1		; Port P12 direction bit
pd1_3			.btequ		3,pd1		; Port P13 direction bit
pd1_4			.btequ		4,pd1		; Port P14 direction bit
pd1_5			.btequ		5,pd1		; Port P15 direction bit
pd1_6			.btequ		6,pd1		; Port P16 direction bit
pd1_7			.btequ		7,pd1		; Port P17 direction bit
;
p2				.equ		00e4h
p2_0			.btequ		0,p2		; Port P20 bit
p2_1			.btequ		1,p2		; Port P21 bit
p2_2			.btequ		2,p2		; Port P22 bit
p2_3			.btequ		3,p2		; Port P23 bit
p2_4			.btequ		4,p2		; Port P24 bit
p2_5			.btequ		5,p2		; Port P25 bit
p2_6			.btequ		6,p2		; Port P26 bit
p2_7			.btequ		7,p2		; Port P27 bit
;
pd2				.equ		00e6h
pd2_0			.btequ		0,pd2		; Port P20 direction bit
pd2_1			.btequ		1,pd2		; Port P21 direction bit
pd2_2			.btequ		2,pd2		; Port P22 direction bit
pd2_3			.btequ		3,pd2		; Port P23 direction bit
pd2_4			.btequ		4,pd2		; Port P24 direction bit
pd2_5			.btequ		5,pd2		; Port P25 direction bit
pd2_6			.btequ		6,pd2		; Port P26 direction bit
pd2_7			.btequ		7,pd2		; Port P27 direction bit
;
p3				.equ		00e5h
p3_0			.btequ		0,p3		; Port P30 bit
p3_1			.btequ		1,p3		; Port P31 bit
p3_2			.btequ		2,p3		; Port P32 bit
p3_3			.btequ		3,p3		; Port P33 bit
p3_4			.btequ		4,p3		; Port P34 bit
p3_5			.btequ		5,p3		; Port P35 bit
p3_6			.btequ		6,p3		; Port P36 bit
p3_7			.btequ		7,p3		; Port P37 bit
;
pd3				.equ		00e7h
pd3_0			.btequ		0,pd3		; Port P30 direction bit
pd3_1			.btequ		1,pd3		; Port P31 direction bit
pd3_2			.btequ		2,pd3		; Port P32 direction bit
pd3_3			.btequ		3,pd3		; Port P33 direction bit
pd3_4			.btequ		4,pd3		; Port P34 direction bit
pd3_5			.btequ		5,pd3		; Port P35 direction bit
pd3_6			.btequ		6,pd3		; Port P36 direction bit
pd3_7			.btequ		7,pd3		; Port P37 direction bit
;
p4				.equ		00e8h
p4_3			.btequ		3,p4		; Port P43 bit
p4_4			.btequ		4,p4		; Port P44 bit
p4_5			.btequ		5,p4		; Port P45 bit
p4_6			.btequ		6,p4		; Port P46 bit
p4_7			.btequ		7,p4		; Port P47 bit
;
pd4				.equ		00eah
pd4_3			.btequ		3,pd4		; Port P43 direction bit
pd4_4			.btequ		4,pd4		; Port P44 direction bit
pd4_5			.btequ		5,pd4		; Port P45 direction bit
;
p5				.equ		00e9h
p5_0			.btequ		0,p5		; Port P50 bit
p5_1			.btequ		1,p5		; Port P51 bit
p5_2			.btequ		2,p5		; Port P52 bit
p5_3			.btequ		3,p5		; Port P53 bit
p5_4			.btequ		4,p5		; Port P54 bit
p5_5			.btequ		5,p5		; Port P55 bit
p5_6			.btequ		6,p5		; Port P56 bit
p5_7			.btequ		7,p5		; Port P57 bit
;
pd5				.equ		00ebh
pd5_0			.btequ		0,pd5		; Port P50 direction bit
pd5_1			.btequ		1,pd5		; Port P51 direction bit
pd5_2			.btequ		2,pd5		; Port P52 direction bit
pd5_3			.btequ		3,pd5		; Port P53 direction bit
pd5_4			.btequ		4,pd5		; Port P54 direction bit
pd5_5			.btequ		5,pd5		; Port P55 direction bit
pd5_6			.btequ		6,pd5		; Port P56 direction bit
pd5_7			.btequ		7,pd5		; Port P57 direction bit
;
p6				.equ		00ech
p6_0			.btequ		0,p6		; Port P60 bit
p6_1			.btequ		1,p6		; Port P61 bit
p6_2			.btequ		2,p6		; Port P62 bit
p6_3			.btequ		3,p6		; Port P63 bit
p6_4			.btequ		4,p6		; Port P64 bit
p6_5			.btequ		5,p6		; Port P65 bit
p6_6			.btequ		6,p6		; Port P66 bit
p6_7			.btequ		7,p6		; Port P67 bit
;
pd6				.equ		00eeh
pd6_0			.btequ		0,pd6		; Port P60 direction bit
pd6_1			.btequ		1,pd6		; Port P61 direction bit
pd6_2			.btequ		2,pd6		; Port P62 direction bit
pd6_3			.btequ		3,pd6		; Port P63 direction bit
pd6_4			.btequ		4,pd6		; Port P64 direction bit
pd6_5			.btequ		5,pd6		; Port P65 direction bit
pd6_6			.btequ		6,pd6		; Port P66 direction bit
pd6_7			.btequ		7,pd6		; Port P67 direction bit
;
p7				.equ		02e2h
p7_0			.btequ		0,p7		; Port P70 bit
p7_1			.btequ		1,p7		; Port P71 bit
p7_2			.btequ		2,p7		; Port P72 bit
p7_3			.btequ		3,p7		; Port P73 bit
p7_4			.btequ		4,p7		; Port P74 bit
p7_5			.btequ		5,p7		; Port P75 bit
p7_6			.btequ		6,p7		; Port P76 bit
p7_7			.btequ		7,p7		; Port P77 bit
;
pd7				.equ		02e0h
pd7_0			.btequ		0,pd7		; Port P70 direction bit
pd7_1			.btequ		1,pd7		; Port P71 direction bit
pd7_2			.btequ		2,pd7		; Port P72 direction bit
pd7_3			.btequ		3,pd7		; Port P73 direction bit
pd7_4			.btequ		4,pd7		; Port P74 direction bit
pd7_5			.btequ		5,pd7		; Port P75 direction bit
pd7_6			.btequ		6,pd7		; Port P76 direction bit
pd7_7			.btequ		7,pd7		; Port P77 direction bit
;
p8				.equ		02e6h
p8_0			.btequ		0,p8		; Port P80 bit
p8_1			.btequ		1,p8		; Port P81 bit
p8_2			.btequ		2,p8		; Port P82 bit
p8_3			.btequ		3,p8		; Port P83 bit
p8_4			.btequ		4,p8		; Port P84 bit
p8_5			.btequ		5,p8		; Port P85 bit
p8_6			.btequ		6,p8		; Port P86 bit
p8_7			.btequ		7,p8		; Port P87 bit
;
pd8				.equ		02e4h
pd8_0			.btequ		0,pd8		; Port P80 direction bit
pd8_1			.btequ		1,pd8		; Port P81 direction bit
pd8_2			.btequ		2,pd8		; Port P82 direction bit
pd8_3			.btequ		3,pd8		; Port P83 direction bit
pd8_4			.btequ		4,pd8		; Port P84 direction bit
pd8_5			.btequ		5,pd8		; Port P85 direction bit
pd8_6			.btequ		6,pd8		; Port P86 direction bit
pd8_7			.btequ		7,pd8		; Port P87 direction bit
;
p9				.equ		02e7h
p9_0			.btequ		0,p9		; Port P90 bit
p9_1			.btequ		1,p9		; Port P91 bit
p9_2			.btequ		2,p9		; Port P92 bit
p9_3			.btequ		3,p9		; Port P93 bit
;
pd9				.equ		02e5h
pd9_0			.btequ		0,pd9		; Port P90 direction bit
pd9_1			.btequ		1,pd9		; Port P91 direction bit
pd9_2			.btequ		2,pd9		; Port P92 direction bit
pd9_3			.btequ		3,pd9		; Port P93 direction bit
;
;-------------------------------------------------------
;   Port P2 drive capacity control register
;-------------------------------------------------------
p2drr			.equ		00f4h
p2drr0			.btequ		0,p2drr		; P20 drive capacity
p2drr1			.btequ		1,p2drr		; P21 drive capacity
p2drr2			.btequ		2,p2drr		; P22 drive capacity
p2drr3			.btequ		3,p2drr		; P23 drive capacity
p2drr4			.btequ		4,p2drr		; P24 drive capacity
p2drr5			.btequ		5,p2drr		; P25 drive capacity
p2drr6			.btequ		6,p2drr		; P26 drive capacity
p2drr7			.btequ		7,p2drr		; P27 drive capacity
;
;-------------------------------------------------------
;   UART1 function select register
;-------------------------------------------------------
u1sr			.equ		00f5h
clk10psel		.btequ		2,u1sr		; CLK1 port select bit
clk11psel		.btequ		3,u1sr		; CLK1 port select bit
;
;-------------------------------------------------------
;   Port mode register
;-------------------------------------------------------
pmr				.equ		00f8h
int1sel			.btequ		0,pmr		; INT1 port select bit
int2sel			.btequ		1,pmr		; INT2 port select bit
u1pinsel		.btequ		4,pmr		; UART1 enable bit
iicsel			.btequ		7,pmr		; SSU/IIC bus switch bit
;
;-------------------------------------------------------
;   External input enable register
;-------------------------------------------------------
inten			.equ		00f9h
int0en			.btequ		0,inten		; INT0 input enable bit
int0pl			.btequ		1,inten		; INT0 input polarity select bit
int1en			.btequ		2,inten		; INT1 input enable bit
int1pl			.btequ		3,inten		; INT1 input polarity select bit
int2en			.btequ		4,inten		; INT2 input enable bit
int2pl			.btequ		5,inten		; INT2 input polarity select bit
int3en			.btequ		6,inten		; INT3 input enable bit
int3pl			.btequ		7,inten		; INT3 input polarity select bit
;
;-------------------------------------------------------
;   INT0 input filter select register
;-------------------------------------------------------
intf			.equ		00fah
int0f0			.btequ		0,intf		; INT0 input filter select bit
int0f1			.btequ		1,intf		; INT0 input filter select bit
int1f0			.btequ		2,intf		; INT1 input filter select bit
int1f1			.btequ		3,intf		; INT1 input filter select bit
int2f0			.btequ		4,intf		; INT2 input filter select bit
int2f1			.btequ		5,intf		; INT2 input filter select bit
int3f0			.btequ		6,intf		; INT3 input filter select bit
int3f1			.btequ		7,intf		; INT3 input filter select bit
;
;-------------------------------------------------------
;   Key input enable register
;-------------------------------------------------------
kien			.equ		00fbh
ki0en			.btequ		0,kien		; KI0 input enable bit
ki0pl			.btequ		1,kien		; KI0 input polarity select bit
ki1en			.btequ		2,kien		; KI1 input enable bit
ki1pl			.btequ		3,kien		; KI1 input polarity select bit
ki2en			.btequ		4,kien		; KI2 input enable bit
ki2pl			.btequ		5,kien		; KI2 input polarity select bit
ki3en			.btequ		6,kien		; KI3 input enable bit
ki3pl			.btequ		7,kien		; KI3 input polarity select bit
;
;-------------------------------------------------------
;   Pull-up control registers
;-------------------------------------------------------
pur0			.equ		00fch
pu00			.btequ		0,pur0		; P00 to P03 pull-up
pu01			.btequ		1,pur0		; P04 to P07 pull-up
pu02			.btequ		2,pur0		; P10 to P13 pull-up
pu03			.btequ		3,pur0		; P14 to P17 pull-up
pu04			.btequ		4,pur0		; P20 to P23 pull-up
pu05			.btequ		5,pur0		; P24 to P27 pull-up
pu06			.btequ		6,pur0		; P30 to P33 pull-up
pu07			.btequ		7,pur0		; P34 to P37 pull-up
;
pur1			.equ		00fdh
pu10			.btequ		0,pur1		; P43 pull-up
pu11			.btequ		1,pur1		; P44, P45 pull-up
pu12			.btequ		2,pur1		; P50, P53 pull-up
pu13			.btequ		3,pur1		; P54, P57 pull-up
pu14			.btequ		4,pur1		; P60 to P63 pull-up
pu15			.btequ		5,pur1		; P64 to P67 pull-up
;
pur2			.equ		02fch
pu20			.btequ		0,pur2		; P70 to P73 pull-up
pu21			.btequ		1,pur2		; P74 to P77 pull-up
pu22			.btequ		2,pur2		; P80 to P83 pull-up
pu23			.btequ		3,pur2		; P84 to P87 pull-up
pu24			.btequ		4,pur2		; P90 to P93 pull-up
;
;-------------------------------------------------------
;   Timer RA control register
;-------------------------------------------------------
tracr			.equ		0100h
tstart_tracr	.btequ		0,tracr		; Timer RA count start bit
tcstf_tracr		.btequ		1,tracr		; Timer RA count status flag
tstop_tracr		.btequ		2,tracr		; Timer RA count forcible stop bit
tedgf_tracr		.btequ		4,tracr		; Active edge judgment flag
tundf_tracr		.btequ		5,tracr		; Timer RA underflow flag
;
;-------------------------------------------------------
;   Timer RA I/O control register
;-------------------------------------------------------
traioc			.equ		0101h
tedgsel_traioc	.btequ		0,traioc	; TRAIO polarity switch bit
topcr_traioc	.btequ		1,traioc	; TRAIO output control bit
toena_traioc	.btequ		2,traioc	; TRAO output enable bit
tiosel_traioc	.btequ		3,traioc	; INT1/TRAIO select bit
tipf0_traioc	.btequ		4,traioc	; TRAIO input filter select bit
tipf1_traioc	.btequ		5,traioc	; TRAIO input filter select bit
;
;-------------------------------------------------------
;   Timer RA mode register
;-------------------------------------------------------
tramr			.equ		0102h
tmod0_tramr		.btequ		0,tramr		; Timer RA operation mode select bit
tmod1_tramr		.btequ		1,tramr		; Timer RA operation mode select bit
tmod2_tramr		.btequ		2,tramr		; Timer RA operation mode select bit
tck0_tramr		.btequ		4,tramr		; Timer RA count source select bit
tck1_tramr		.btequ		5,tramr		; Timer RA count source select bit
tck2_tramr		.btequ		6,tramr		; Timer RA count source select bit
tckcut_tramr	.btequ		7,tramr		; Timer RA count source cutoff bit
;
;-------------------------------------------------------
;   Timer RA prescaler register
;-------------------------------------------------------
trapre			.equ		0103h
;
;-------------------------------------------------------
;   Timer RA register
;-------------------------------------------------------
tra				.equ		0104h
;
;-------------------------------------------------------
;   LIN special function register
;-------------------------------------------------------
lincr2			.equ		0105h
;
bce_lincr2	.btequ		0,lincr2		; When Synch Break send, bus collision detection effective bit
;
;-------------------------------------------------------
;   LIN control register
;-------------------------------------------------------
lincr			.equ		0106h
sfie_lincr		.btequ		0,lincr		; Synchronous field measurementcompleted interrupt enable bit
sbie_lincr		.btequ		1,lincr		; Synchronous break detection interrupt enable bit
bcie_lincr		.btequ		2,lincr		; Bus collision detection interrupt enable bit
rxdsf_lincr		.btequ		3,lincr		; RxD0 input status flag
lstart_lincr	.btequ		4,lincr		; Synchronous Break detection start bit
sbe_lincr		.btequ		5,lincr		; RxD0 input unmasking timing select bit
mst_lincr		.btequ		6,lincr		; LIN operation mode setting bit
line_lincr		.btequ		7,lincr		; LIN operation start bit
;
;-------------------------------------------------------
;   LIN status register
;-------------------------------------------------------
linst			.equ		0107h
sfdct_linst		.btequ		0,linst		; Synchronous field measurementcompleted flag
sbdct_linst		.btequ		1,linst		; Synchronous break detection flag
bcdct_linst		.btequ		2,linst		; Bus collision detection flag
b0clr_linst		.btequ		3,linst		; SFDCT flag clear bit
b1clr_linst		.btequ		4,linst		; SBDCT flag clear bit
b2clr_linst		.btequ		5,linst		; BCDCT flag clear bit
;
;-------------------------------------------------------
;   Timer RB control register
;-------------------------------------------------------
trbcr			.equ		0108h
tstart_trbcr	.btequ		0,trbcr		; Timer RB count start bit
tcstf_trbcr		.btequ		1,trbcr		; Timer RB count status flag
tstop_trbcr		.btequ		2,trbcr		; Timer RB count forcible stop bit
;
;-------------------------------------------------------
;   Timer RB one shot control register
;-------------------------------------------------------
trbocr			.equ		0109h
tosst_trbocr	.btequ		0,trbocr	; Timer RB one-shot start bit
tossp_trbocr	.btequ		1,trbocr	; Timer RB one-shot stop bit
tosstf_trbocr	.btequ		2,trbocr	; Timer RB one-shot status flag
;
;-------------------------------------------------------
;   Timer RB I/O control register
;-------------------------------------------------------
trbioc			.equ		010ah
topl_trbioc		.btequ		0,trbioc	; Timer RB output level select bit
tocnt_trbioc	.btequ		1,trbioc	; Timer RB output switch bit
inostg_trbioc	.btequ		2,trbioc	; One-shot trigger control bit
inoseg_trbioc	.btequ		3,trbioc	; One-shot trigger polarity select bit
;
;-------------------------------------------------------
;   Timer RB mode register
;-------------------------------------------------------
trbmr			.equ		010bh
tmod0_trbmr		.btequ		0,trbmr		; Timer RB operating mode select bit
tmod1_trbmr		.btequ		1,trbmr		; Timer RB operating mode select bit
twrc_trbmr		.btequ		3,trbmr		; Timer RB write control bit
tck0_trbmr		.btequ		4,trbmr		; Timer RB count source select bit
tck1_trbmr		.btequ		5,trbmr		; Timer RB count source select bit
tckcut_trbmr	.btequ		7,trbmr		; Timer RB count source cutoff bit
;
;-------------------------------------------------------
;   Timer RB prescaler register
;-------------------------------------------------------
trbpre			.equ		010ch
;
;-------------------------------------------------------
;   Timer RB secondary register
;-------------------------------------------------------
trbsc			.equ		010dh
;
;-------------------------------------------------------
;   Timer RB Primary Register
;-------------------------------------------------------
trbpr			.equ		010eh
;
;-------------------------------------------------------
;   Timer RE seconds data register / Timer RE counter data register
;-------------------------------------------------------
tresec			.equ		0118h
sc00_tresec		.btequ		0,tresec	; 1st digit of seconds count bits
sc01_tresec		.btequ		1,tresec	; 1st digit of seconds count bits
sc02_tresec		.btequ		2,tresec	; 1st digit of seconds count bits
sc03_tresec		.btequ		3,tresec	; 1st digit of seconds count bits
sc10_tresec		.btequ		4,tresec	; 2nd digit of seconds count bits
sc11_tresec		.btequ		5,tresec	; 2nd digit of seconds count bits
sc12_tresec		.btequ		6,tresec	; 2nd digit of seconds count bits
bsy_tresec		.btequ		7,tresec	; Timer RE busy flag
;
;-------------------------------------------------------
;   Timer RE minutes data register / Timer RE compare data register
;-------------------------------------------------------
tremin			.equ		0119h
mn00_tremin		.btequ		0,tremin	; 1st digit of minutes count bits
mn01_tremin		.btequ		1,tremin	; 1st digit of minutes count bits
mn02_tremin		.btequ		2,tremin	; 1st digit of minutes count bits
mn03_tremin		.btequ		3,tremin	; 1st digit of minutes count bits
mn10_tremin		.btequ		4,tremin	; 2nd digit of minutes count bits
mn11_tremin		.btequ		5,tremin	; 2nd digit of minutes count bits
mn12_tremin		.btequ		6,tremin	; 2nd digit of minutes count bits
bsy_tremin		.btequ		7,tremin	; Timer RE busy flag
;
;-------------------------------------------------------
;   Timer RE Hours Data Register
;-------------------------------------------------------
trehr			.equ		011ah
hr00_trehr		.btequ		0,trehr		; 1st digit of hours count bits
hr01_trehr		.btequ		1,trehr		; 1st digit of hours count bits
hr02_trehr		.btequ		2,trehr		; 1st digit of hours count bits
hr03_trehr		.btequ		3,trehr		; 1st digit of hours count bits
hr10_trehr		.btequ		4,trehr		; 2nd digit of hours count bits
hr11_trehr		.btequ		5,trehr		; 2nd digit of hours count bits
bsy_trehr		.btequ		7,trehr		; Timer RE busy flag
;
;-------------------------------------------------------
;   Timer RE Days of Week Data Register
;-------------------------------------------------------
trewk			.equ		011bh
wk0_trewk		.btequ		0,trewk		; Days of week count bits
wk1_trewk		.btequ		1,trewk		; Days of week count bits
wk2_trewk		.btequ		2,trewk		; Days of week count bits
bsy_trewk		.btequ		7,trewk		; Timer RE busy flag
;
;-------------------------------------------------------
;   Timer RE control register1
;-------------------------------------------------------
trecr1			.equ		011ch
tcstf_trecr1	.btequ		1,trecr1	; Timer RE count status flag
toena_trecr1	.btequ		2,trecr1	; TREO pin output enable bit
int_trecr1		.btequ		3,trecr1	; Interrupt request timing bit
trerst_trecr1	.btequ		4,trecr1	; Timer RE reset bit
pm_trecr1		.btequ		5,trecr1	; A.M. / P.M. bit
h12_h24_trecr1	.btequ		6,trecr1	; Operating mode select bit
tstart_trecr1	.btequ		7,trecr1	; Timer RE count start bit
;
;-------------------------------------------------------
;   Timer RE control register2
;-------------------------------------------------------
trecr2			.equ		011dh
seie_trecr2		.btequ		0,trecr2	; Periodic interrupt triggered every second enable bit
mnie_trecr2		.btequ		1,trecr2	; Periodic interrupt triggered every minute enable bit
hrie_trecr2		.btequ		2,trecr2	; Periodic interrupt triggered every hour enable bit
dyie_trecr2		.btequ		3,trecr2	; Periodic interrupt triggered every day enable bit
wkie_trecr2		.btequ		4,trecr2	; Periodic interrupt triggered every week enable bit
comie_trecr2	.btequ		5,trecr2	; Compare match interrupt enable bit
;
;-------------------------------------------------------
;   Timer RE count source select register
;-------------------------------------------------------
trecsr			.equ		011eh
rcs0_trecsr		.btequ		0,trecsr	; Count source select bit
rcs1_trecsr		.btequ		1,trecsr	; Count source select bit
rcs2_trecsr		.btequ		2,trecsr	; 4-Bit counter select bit
rcs3_trecsr		.btequ		3,trecsr	; Real-Time clock mode select bit
rcs5_trecsr		.btequ		5,trecsr	; Clock output select bit
rcs6_trecsr		.btequ		6,trecsr	; Clock output select bit
;
;-------------------------------------------------------
;   Timer RC mode register
;-------------------------------------------------------
trcmr			.equ		0120h
pwmb_trcmr		.btequ		0,trcmr		; TRCIOB PWM mode select bit
pwmc_trcmr		.btequ		1,trcmr		; TRCIOC PWM mode select bit
pwmd_trcmr		.btequ		2,trcmr		; TRCIOD PWM mode select bit
pwm2_trcmr		.btequ		3,trcmr		; PWM2 mode select bit
bfc_trcmr		.btequ		4,trcmr		; TRCGRC register function selection bit
bfd_trcmr		.btequ		5,trcmr		; TRCGRD register function selection bit
tstart_trcmr	.btequ		7,trcmr		; TRC count start bit
;
;-------------------------------------------------------
;   Timer RC control register 1
;-------------------------------------------------------
trccr1			.equ		0121h
toa_trccr1		.btequ		0,trccr1	; TRCIOA output level select bit
tob_trccr1		.btequ		1,trccr1	; TRCIOB output level select bit
toc_trccr1		.btequ		2,trccr1	; TRCIOC output level select bit
tod_trccr1		.btequ		3,trccr1	; TRCIOD output level select bit
tck0_trccr1		.btequ		4,trccr1	; Count source selection bit
tck1_trccr1		.btequ		5,trccr1	; Count source selection bit
tck2_trccr1		.btequ		6,trccr1	; Count source selection bit
cclr_trccr1		.btequ		7,trccr1	; TRC counter clear select bit
;
;-------------------------------------------------------
;   Timer RC interrupt enable register
;-------------------------------------------------------
trcier			.equ		0122h
imiea_trcier	.btequ		0,trcier	; Input capture / compare match interrupt enable bit A
imieb_trcier	.btequ		1,trcier	; Input capture / compare match interrupt enable bit B
imiec_trcier	.btequ		2,trcier	; Input capture / compare match interrupt enable bit C
imied_trcier	.btequ		3,trcier	; Input capture / compare match interrupt enable bit D
ovie_trcier		.btequ		7,trcier	; Overflow / underflow interrupt enable bit
;
;-------------------------------------------------------
;   Timer RC status register
;-------------------------------------------------------
trcsr			.equ		0123h
imfa_trcsr		.btequ		0,trcsr		; Input capture / compare match flag A
imfb_trcsr		.btequ		1,trcsr		; Input capture / compare match flag B
imfc_trcsr		.btequ		2,trcsr		; Input capture / compare match flag C
imfd_trcsr		.btequ		3,trcsr		; Input capture / compare match flag D
ovf_trcsr		.btequ		7,trcsr		; Overflow flag
;
;-------------------------------------------------------
;   Timer RC I/O contorol register 0
;-------------------------------------------------------
trcior0			.equ		0124h
ioa0_trcior0	.btequ		0,trcior0	; TRCGRA control bit
ioa1_trcior0	.btequ		1,trcior0	; TRCGRA control bit
ioa2_trcior0	.btequ		2,trcior0	; TRCGRA mode selection bit
iob0_trcior0	.btequ		4,trcior0	; TRCGRB control bit
iob1_trcior0	.btequ		5,trcior0	; TRCGRB control bit
iob2_trcior0	.btequ		6,trcior0	; TRCGRB mode selection bit
;
;-------------------------------------------------------
;   Timer RC I/O contorol register 1
;-------------------------------------------------------
trcior1			.equ		0125h
ioc0_trcior1	.btequ		0,trcior1	; TRCGRC control bit
ioc1_trcior1	.btequ		1,trcior1	; TRCGRC control bit
ioc2_trcior1	.btequ		2,trcior1	; TRCGRC mode selection bit
iod0_trcior1	.btequ		4,trcior1	; TRCGRD control bit
iod1_trcior1	.btequ		5,trcior1	; TRCGRD control bit
iod2_trcior1	.btequ		6,trcior1	; TRCGRD mode selection bit
;
;-------------------------------------------------------
;   Timer RC Counter , Timer RC general register A,B,C,D
;-------------------------------------------------------
trc				.equ		0126h		; Timer RC counter
trcgra			.equ		0128h		; Timer RC general register A
trcgrb			.equ		012ah		; Timer RC general register B
trcgrc			.equ		012ch		; Timer RC general register C
trcgrd			.equ		012eh		; Timer RC general register D
;
;-------------------------------------------------------
;   Timer RC control register 2
;-------------------------------------------------------
trccr2			.equ		0130h
csel_trccr2		.btequ		5,trccr2	; Timer RC operating mode select bit
tceg0_trccr2	.btequ		6,trccr2	; TRCTRG input edge selection bit
tceg1_trccr2	.btequ		7,trccr2	; TRCTRG input edge selection bit
;
;-------------------------------------------------------
;   Timer RC digital filter function selection register
;-------------------------------------------------------
trcdf			.equ		0131h
dfa_trcdf		.btequ		0,trcdf		; TRCIOA pin digital filter function selection bit
dfb_trcdf		.btequ		1,trcdf		; TRCIOB pin digital filter function selection bit
dfc_trcdf		.btequ		2,trcdf		; TRCIOC pin digital filter function selection bit
dfd_trcdf		.btequ		3,trcdf		; TRCIOD pin digital filter function selection bit
dftrg_trcdf		.btequ		4,trcdf		; TRCIOG pin digital filter function selection bit
dfck0_trcdf		.btequ		6,trcdf		; Clock selection bit for digital filter function
dfck1_trcdf		.btequ		7,trcdf		; Clock selection bit for digital filter function
;
;-------------------------------------------------------
;   Timer RC output master enable register
;-------------------------------------------------------
trcoer			.equ		0132h
ea_trcoer		.btequ		0,trcoer	; TRCIOA output disable bit
eb_trcoer		.btequ		1,trcoer	; TRCIOB output disable bit
ec_trcoer		.btequ		2,trcoer	; TRCIOC output disable bit
ed_trcoer		.btequ		3,trcoer	; TRCIOD output disable bit
pto_trcoer		.btequ		7,trcoer	; INT0 of pulse output forced cutoff signal input enabled bit
;
;-------------------------------------------------------
;   Timer RD start register
;-------------------------------------------------------
trdstr			.equ		0137h
tstart0_trdstr	.btequ		0,trdstr	; TRD0 count start bit
tstart1_trdstr	.btequ		1,trdstr	; TRD1 count start bit
csel0_trdstr	.btequ		2,trdstr	; TRD0 count operation select bit
csel1_trdstr	.btequ		3,trdstr	; TRD1 count operation select bit
;
;-------------------------------------------------------
;   Timer RD mode register
;-------------------------------------------------------
trdmr			.equ		0138h
sync_trdmr		.btequ		0,trdmr		; Timer RD synchronous bit
bfc0_trdmr		.btequ		4,trdmr		; TRDGRC0 register function selection bit
bfd0_trdmr		.btequ		5,trdmr		; TRDGRD0 register function selection bit
bfc1_trdmr		.btequ		6,trdmr		; TRDGRC1 register function selection bit
bfd1_trdmr		.btequ		7,trdmr		; TRDGRD1 register function selection bit
;
;-------------------------------------------------------
;   Timer RD PWM mode register
;-------------------------------------------------------
trdpmr			.equ		0139h
pwmb0_trdpmr	.btequ		0,trdpmr	; PWM mode of TRDIOB0 selection bit
pwmc0_trdpmr	.btequ		1,trdpmr	; PWM mode of TRDIOC0 selection bit
pwmd0_trdpmr	.btequ		2,trdpmr	; PWM mode of TRDIOD0 selection bit
pwmb1_trdpmr	.btequ		4,trdpmr	; PWM mode of TRDIOB1 selection bit
pwmc1_trdpmr	.btequ		5,trdpmr	; PWM mode of TRDIOC1 selection bit
pwmd1_trdpmr	.btequ		6,trdpmr	; PWM mode of TRDIOD1 selection bit
;
;-------------------------------------------------------
;   Timer RD function control register
;-------------------------------------------------------
trdfcr			.equ		013ah
cmd0_trdfcr		.btequ		0,trdfcr	; Combination mode selection bit
cmd1_trdfcr		.btequ		1,trdfcr	; Combination mode selection bit
ols0_trdfcr		.btequ		2,trdfcr	; Normal-Phase output level selection bit
ols1_trdfcr		.btequ		3,trdfcr	; Counter-Phase output level selection bit
adtrg_trdfcr	.btequ		4,trdfcr	; A/D trigger enable bit
adeg_trdfcr		.btequ		5,trdfcr	; A/D trigger edge selection bit
stclk_trdfcr	.btequ		6,trdfcr	; External clock input selection bit
pwm3_trdfcr		.btequ		7,trdfcr	; PWM3 mode selection bit
;
;-------------------------------------------------------
;   Timer RD output master enable register 1
;-------------------------------------------------------
trdoer1			.equ		013bh
ea0_trdoer1		.btequ		0,trdoer1	; TRDIOA0 output disable bit
eb0_trdoer1		.btequ		1,trdoer1	; TRDIOB0 output disable bit
ec0_trdoer1		.btequ		2,trdoer1	; TRDIOC0 output disable bit
ed0_trdoer1		.btequ		3,trdoer1	; TRDIOD0 output disable bit
ea1_trdoer1		.btequ		4,trdoer1	; TRDIOA1 output disable bit
eb1_trdoer1		.btequ		5,trdoer1	; TRDIOB1 output disable bit
ec1_trdoer1		.btequ		6,trdoer1	; TRDIOC1 output disable bit
ed1_trdoer1		.btequ		7,trdoer1	; TRDIOD1 output disable bit
;
;-------------------------------------------------------
;   Timer RD output master enable register 2
;-------------------------------------------------------
trdoer2			.equ		013ch
pto_trdoer2		.btequ		7,trdoer2	; INT0 of pulse output forced cutoff signal input enabled bit
;
;-------------------------------------------------------
;   Timer RD output control register
;-------------------------------------------------------
trdocr			.equ		013dh
toa0_trdocr		.btequ		0,trdocr	; TRDIOA0 output level selection bit
tob0_trdocr		.btequ		1,trdocr	; TRDIOB0 output level selection bit
toc0_trdocr		.btequ		2,trdocr	; TRDIOC0 initial output level selection bit
tod0_trdocr		.btequ		3,trdocr	; TRDIOD0 initial output level selection bit
toa1_trdocr		.btequ		4,trdocr	; TRDIOA1 initial output level selection bit
tob1_trdocr		.btequ		5,trdocr	; TRDIOB1 initial output level selection bit
toc1_trdocr		.btequ		6,trdocr	; TRDIOC1 initial output level selection bit
tod1_trdocr		.btequ		7,trdocr	; TRDIOD1 initial output level selection bit
;
;-------------------------------------------------------
;   Timer RD digital filter function selection register 0
;-------------------------------------------------------
trddf0			.equ		013eh
dfa_trddf0		.btequ		0,trddf0	; TRDIOA pin digital filter function selection bit
dfb_trddf0		.btequ		1,trddf0	; TRDIOB pin digital filter function selection bit
dfc_trddf0		.btequ		2,trddf0	; TRDIOC pin digital filter function selection bit
dfd_trddf0		.btequ		3,trddf0	; TRDIOD pin digital filter function selection bit
dfck0_trddf0	.btequ		6,trddf0	; Clock selection bit for digital filter function
dfck1_trddf0	.btequ		7,trddf0	; Clock selection bit for digital filter function
;
;-------------------------------------------------------
;   Timer RD digital filter function selection register 1
;-------------------------------------------------------
trddf1			.equ		013fh
dfa_trddf1		.btequ		0,trddf1	; TRDIOA pin digital filter function selection bit
dfb_trddf1		.btequ		1,trddf1	; TRDIOB pin digital filter function selection bit
dfc_trddf1		.btequ		2,trddf1	; TRDIOC pin digital filter function selection bit
dfd_trddf1		.btequ		3,trddf1	; TRDIOD pin digital filter function selection bit
dfck0_trddf1	.btequ		6,trddf1	; Clock selection bit for digital filter function
dfck1_trddf1	.btequ		7,trddf1	; Clock selection bit for digital filter function
;
;-------------------------------------------------------
;   Timer RD control register 0
;-------------------------------------------------------
trdcr0			.equ		0140h
tck0_trdcr0		.btequ		0,trdcr0	; Count source selection bit
tck1_trdcr0		.btequ		1,trdcr0	; Count source selection bit
tck2_trdcr0		.btequ		2,trdcr0	; Count source selection bit
ckeg0_trdcr0	.btequ		3,trdcr0	; External clock edge selection bit
ckeg1_trdcr0	.btequ		4,trdcr0	; External clock edge selection bit
cclr0_trdcr0	.btequ		5,trdcr0	; TRD0 counter clear selection bit
cclr1_trdcr0	.btequ		6,trdcr0	; TRD0 counter clear selection bit
cclr2_trdcr0	.btequ		7,trdcr0	; TRD0 counter clear selection bit
;
;-------------------------------------------------------
;   Timer RD control register 1
;-------------------------------------------------------
trdcr1			.equ		0150h
tck0_trdcr1		.btequ		0,trdcr1	; Count source selection bit
tck1_trdcr1		.btequ		1,trdcr1	; Count source selection bit
tck2_trdcr1		.btequ		2,trdcr1	; Count source selection bit
ckeg0_trdcr1	.btequ		3,trdcr1	; External clock edge selection bit
ckeg1_trdcr1	.btequ		4,trdcr1	; External clock edge selection bit
cclr0_trdcr1	.btequ		5,trdcr1	; TRD1 counter clear selection bit
cclr1_trdcr1	.btequ		6,trdcr1	; TRD1 counter clear selection bit
cclr2_trdcr1	.btequ		7,trdcr1	; TRD1 counter clear selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register A0
;-------------------------------------------------------
trdiora0		.equ		0141h
ioa0_trdiora0	.btequ		0,trdiora0	; TRDGRA control bit
ioa1_trdiora0	.btequ		1,trdiora0	; TRDGRA control bit
ioa2_trdiora0	.btequ		2,trdiora0	; TRDGRA mode selection bit
ioa3_trdiora0	.btequ		3,trdiora0	; Input capture input switch bit
iob0_trdiora0	.btequ		4,trdiora0	; TRDGRB control bit
iob1_trdiora0	.btequ		5,trdiora0	; TRDGRB control bit
iob2_trdiora0	.btequ		6,trdiora0	; TRDGRB mode selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register A1
;-------------------------------------------------------
trdiora1		.equ		0151h
ioa0_trdiora1	.btequ		0,trdiora1	; TRDGRA control bit
ioa1_trdiora1	.btequ		1,trdiora1	; TRDGRA control bit
ioa2_trdiora1	.btequ		2,trdiora1	; TRDGRA mode selection bit
ioa3_trdiora1	.btequ		3,trdiora1	; Input capture input switch bit
iob0_trdiora1	.btequ		4,trdiora1	; TRDGRB control bit
iob1_trdiora1	.btequ		5,trdiora1	; TRDGRB control bit
iob2_trdiora1	.btequ		6,trdiora1	; TRDGRB mode selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register C0
;-------------------------------------------------------
trdiorc0		.equ		0142h
ioc0_trdiorc0	.btequ		0,trdiorc0	; TRDGRC control bit
ioc1_trdiorc0	.btequ		1,trdiorc0	; TRDGRC control bit
ioc2_trdiorc0	.btequ		2,trdiorc0	; TRDGRC mode selection bit
ioc3_trdiorc0	.btequ		3,trdiorc0	; TRDGRC register function selection bit
iod0_trdiorc0	.btequ		4,trdiorc0	; TRDGRD control bit
iod1_trdiorc0	.btequ		5,trdiorc0	; TRDGRD control bit
iod2_trdiorc0	.btequ		6,trdiorc0	; TRDGRD mode selection bit
iod3_trdiorc0	.btequ		7,trdiorc0	; TRDGRD register function selection bit
;
;-------------------------------------------------------
;   Timer RD I/O control register C1
;-------------------------------------------------------
trdiorc1		.equ		0152h
ioc0_trdiorc1	.btequ		0,trdiorc1	; TRDGRC control bit
ioc1_trdiorc1	.btequ		1,trdiorc1	; TRDGRC control bit
ioc2_trdiorc1	.btequ		2,trdiorc1	; TRDGRC mode selection bit
ioc3_trdiorc1	.btequ		3,trdiorc1	; TRDGRC register function selection bit
iod0_trdiorc1	.btequ		4,trdiorc1	; TRDGRD control bit
iod1_trdiorc1	.btequ		5,trdiorc1	; TRDGRD control bit
iod2_trdiorc1	.btequ		6,trdiorc1	; TRDGRD mode selection bit
iod3_trdiorc1	.btequ		7,trdiorc1	; TRDGRD register function selection bit
;
;-------------------------------------------------------
;   Timer RD status register 0
;-------------------------------------------------------
trdsr0			.equ		0143h
imfa_trdsr0		.btequ		0,trdsr0	; Input capture / compare match flag A
imfb_trdsr0		.btequ		1,trdsr0	; Input capture / compare match flag B
imfc_trdsr0		.btequ		2,trdsr0	; Input capture / compare match flag C
imfd_trdsr0		.btequ		3,trdsr0	; Input capture / compare match flag D
ovf_trdsr0		.btequ		4,trdsr0	; Overflow flag
;
;-------------------------------------------------------
;   Timer RD status register 1
;-------------------------------------------------------
trdsr1			.equ		0153h
imfa_trdsr1		.btequ		0,trdsr1	; Input capture / compare match flag A
imfb_trdsr1		.btequ		1,trdsr1	; Input capture / compare match flag B
imfc_trdsr1		.btequ		2,trdsr1	; Input capture / compare match flag C
imfd_trdsr1		.btequ		3,trdsr1	; Input capture / compare match flag D
ovf_trdsr1		.btequ		4,trdsr1	; Overflow flag
udf_trdsr1		.btequ		5,trdsr1	; Underflow flag
;
;-------------------------------------------------------
;   Timer RD interrupt enable register 0
;-------------------------------------------------------
trdier0			.equ		0144h
imiea_trdier0	.btequ		0,trdier0	; Input capture / compare match interrupt enable bit A
imieb_trdier0	.btequ		1,trdier0	; Input capture / compare match interrupt enable bit B
imiec_trdier0	.btequ		2,trdier0	; Input capture / compare match interrupt enable bit C
imied_trdier0	.btequ		3,trdier0	; Input capture / compare match interrupt enable bit D
ovie_trdier0	.btequ		4,trdier0	; Overflow / underflow interrupt enable bit
;
;-------------------------------------------------------
;   Timer RD interrupt enable register 1
;-------------------------------------------------------
trdier1			.equ		0154h
imiea_trdier1	.btequ		0,trdier1	; Input capture / compare match interrupt enable bit A
imieb_trdier1	.btequ		1,trdier1	; Input capture / compare match interrupt enable bit B
imiec_trdier1	.btequ		2,trdier1	; Input capture / compare match interrupt enable bit C
imied_trdier1	.btequ		3,trdier1	; Input capture / compare match interrupt enable bit D
ovie_trdier1	.btequ		4,trdier1	; Overflow / underflow interrupt enable bit
;
;-------------------------------------------------------
;   Timer RD PWM mode output level control register 0
;-------------------------------------------------------
trdpocr0		.equ		0145h
polb_trdpocr0	.btequ		0,trdpocr0	; PWM mode output level control bit B
polc_trdpocr0	.btequ		1,trdpocr0	; PWM mode output level control bit C
pold_trdpocr0	.btequ		2,trdpocr0	; PWM mode output level control bit D
;
;-------------------------------------------------------
;   Timer RD PWM mode output level control register 1
;-------------------------------------------------------
trdpocr1		.equ		0155h
polb_trdpocr1	.btequ		0,trdpocr1	; PWM mode output level control bit B
polc_trdpocr1	.btequ		1,trdpocr1	; PWM mode output level control bit C
pold_trdpocr1	.btequ		2,trdpocr1	; PWM mode output level control bit D
;
;-------------------------------------------------------
;   Timer RD Counter0
;-------------------------------------------------------
trd0			.equ		0146h		; Timer RD counter 0
;
;------------------------------------------------------
;   Timer RD general register A0
;------------------------------------------------------
trdgra0			.equ		0148h		; Timer RD general register A0
;
;------------------------------------------------------
;   Timer RD general register B0
;------------------------------------------------------
trdgrb0			.equ		014ah		; Timer RD general register B0
;
;------------------------------------------------------
;   Timer RD general register C0
;------------------------------------------------------
trdgrc0			.equ		014ch		; Timer RD general register C0
;
;------------------------------------------------------
;   Timer RD general register D0
;------------------------------------------------------
trdgrd0			.equ		014eh		; Timer RD general register D0
;
;------------------------------------------------------
;   Timer RD Counter1
;------------------------------------------------------
trd1			.equ		0156h		; Timer RD counter 1
;
;------------------------------------------------------
;   Timer RD general register A1
;------------------------------------------------------
trdgra1			.equ		0158h		; Timer RD general register A1
;
;------------------------------------------------------
;   Timer RD general register B1
;------------------------------------------------------
trdgrb1			.equ		015ah		; Timer RD general register B1
;
;------------------------------------------------------
;   Timer RD general register C1
;------------------------------------------------------
trdgrc1			.equ		015ch		; Timer RD general register C1
;
;------------------------------------------------------
;   Timer RD general register D1
;------------------------------------------------------
trdgrd1			.equ		015eh		; Timer RD general register D1
;
;-------------------------------------------------------
;   Flash mamory control register4
;-------------------------------------------------------
fmr4			.equ		01b3h
fmr40			.btequ		0,fmr4		; Erase-suspend function enable bit
fmr41			.btequ		1,fmr4		; Erase-suspend request bit
fmr42			.btequ		2,fmr4		; Program-suspend request bit
fmr43			.btequ		3,fmr4		; Erase command flag
fmr44			.btequ		4,fmr4		; Program command flag
fmr46			.btequ		6,fmr4		; Read status flag
fmr47			.btequ		7,fmr4		; Low-Power consumption read mode enable bit
;
;-------------------------------------------------------
;   Flash mamory control register1
;-------------------------------------------------------
fmr1			.equ		01b5h
fmr11			.btequ		1,fmr1		; EW1 mode select bit
fmr15			.btequ		5,fmr1		; Block0 rewrite disable bit
fmr16			.btequ		6,fmr1		; Block1 rewrite disable bit
;
;-------------------------------------------------------
;   Flash mamory control register0
;-------------------------------------------------------
fmr0			.equ		01b7h
fmr00			.btequ		0,fmr0		; RY/BY status flag
fmr01			.btequ		1,fmr0		; CPU rewrite mode select bit
fmr02			.btequ		2,fmr0		; Block 0, 1 rew rite enable bit
fmstp			.btequ		3,fmr0		; Flash memory stop bit
fmr06			.btequ		6,fmr0		; Program status flag 
fmr07			.btequ		7,fmr0		; Erase status flag
;
;-------------------------------------------------------
;   Timer RF register, Capture / Compare register
;-------------------------------------------------------
trf				.equ		0290h		; Timer RF register
trfm0			.equ		029ch		; Capture / Compare0 register
trfm1			.equ		029eh		; Compare1 register
;
;-------------------------------------------------------
;   Timer RF control register 0
;-------------------------------------------------------
trfcr0			.equ		029ah
tstart_trfcr0	.btequ		0,trfcr0	; Timer RF count start bit
tck0_trfcr0		.btequ		1,trfcr0	; Timer RF count source selection bit
tck1_trfcr0		.btequ		2,trfcr0	; Timer RF count source selection bit
trfc03_trfcr0	.btequ		3,trfcr0	; Capture polarity select bit
trfc04_trfcr0	.btequ		4,trfcr0	; Capture polarity select bit
trfc05_trfcr0	.btequ		5,trfcr0	; CMP output selection bit 0 when count stops
trfc06_trfcr0	.btequ		6,trfcr0	; CMP output selection bit 1 when count stops
;
trfc00_trfcr0	.btequ		0,trfcr0	; Timer RF count start bit
trfc01_trfcr0	.btequ		1,trfcr0	; Timer RF count source selection bit
trfc02_trfcr0	.btequ		2,trfcr0	; Timer RF count source selection bit
;
;-------------------------------------------------------
;   Timer RF control register 1
;-------------------------------------------------------
trfcr1			.equ		029bh
tipf0_trfcr1	.btequ		0,trfcr1	; TRFIN filter select bit
tipf1_trfcr1	.btequ		1,trfcr1	; TRFIN filter select bit
cclr_trfcr1		.btequ		2,trfcr1	; TRF register count operation select bit
tmod_trfcr1		.btequ		3,trfcr1	; Timer RF operation mode select bit
trfc14_trfcr1	.btequ		4,trfcr1	; Compare 0 output mode seelct bit
trfc15_trfcr1	.btequ		5,trfcr1	; Compare 0 output mode seelct bit
trfc16_trfcr1	.btequ		6,trfcr1	; Compare 1 output mode seelct bit
trfc17_trfcr1	.btequ		7,trfcr1	; Compare 1 output mode seelct bit
;
trfc10_trfcr1	.btequ		0,trfcr1	; TRFI filter select bit
trfc11_trfcr1	.btequ		1,trfcr1	; TRFI filter select bit
trfc12_trfcr1	.btequ		2,trfcr1	; TRF register count operation select bit
trfc13_trfcr1	.btequ		3,trfcr1	; Timer RF operation mode select bit
;
;-------------------------------------------------------
;   A-D control register2
;-------------------------------------------------------
adcon2			.equ		02d4h
smp				.btequ		0,adcon2	; A-D conversion method select bit
adgsel0			.btequ		3,adcon2	; A-D input group select bit
adgsel1			.btequ		4,adcon2	; A-D input group select bit
;
;-------------------------------------------------------
;   A-D control register0
;-------------------------------------------------------
adcon0			.equ		02d6h
ch0				.btequ		0,adcon0	; Analog input pin select bit
ch1				.btequ		1,adcon0	; Analog input pin select bit
ch2				.btequ		2,adcon0	; Analog input pin select bit
md0				.btequ		3,adcon0	; A-D operation mode select bit
md1				.btequ		4,adcon0	; A-D operation mode select bit
adcap			.btequ		5,adcon0	; A-D conversion automatic start bit
adst			.btequ		6,adcon0	; A-D conversion start flag
cks0			.btequ		7,adcon0	; Frequency select bit0
cks0_adcon0 	.btequ		7,adcon0	; Frequency select bit0
;
;-------------------------------------------------------
;   A-D control register1
;-------------------------------------------------------
adcon1			.equ		02d7h
scan0			.btequ		0,adcon1	; Single sweep mode, Repeat sweep mode, A-D input group select bit
bits			.btequ		3,adcon1	; 8/10-bit mode select bit
cks1			.btequ		4,adcon1	; Frequency select bit1
cks1_adcon1		.btequ		4,adcon1	; Frequency select bit1
vcut			.btequ		5,adcon1	; Vref connect bit
;
;-------------------------------------------------------
;   Timer RF output control register
;-------------------------------------------------------
trfout			.equ		02ffh
trfout0			.btequ		0,trfout	; CMP output enable bit 0
trfout1			.btequ		1,trfout	; CMP output enable bit 1
trfout2			.btequ		2,trfout	; CMP output enable bit 2
trfout3			.btequ		3,trfout	; CMP output enable bit 3
trfout4			.btequ		4,trfout	; CMP output enable bit 4
trfout5			.btequ		5,trfout	; CMP output enable bit 5
trfout6			.btequ		6,trfout	; CMP output enable bit 6
trfout7			.btequ		7,trfout	; CMP output enable bit 7
;
;-------------------------------------------------------
;   Interrupt control register
;-------------------------------------------------------
trcic			.equ		0047h		; Timer RC interrupt control register
ilvl0_trcic		.btequ		0,trcic		; Interrupt priority level select bit
ilvl1_trcic		.btequ		1,trcic		; 
ilvl2_trcic		.btequ		2,trcic		; 
ir_trcic		.btequ		3,trcic		; Interrupt request bit
;
trd0ic			.equ		0048h		; Timer RD 0 interrupt control register
ilvl0_trd0ic	.btequ		0,trd0ic	; Interrupt priority level select bit
ilvl1_trd0ic	.btequ		1,trd0ic	; 
ilvl2_trd0ic	.btequ		2,trd0ic	; 
ir_trd0ic		.btequ		3,trd0ic	; Interrupt request bit
;
trd1ic			.equ		0049h		; Timer RD 1 interrupt control register
ilvl0_trd1ic	.btequ		0,trd1ic	; Interrupt priority level select bit
ilvl1_trd1ic	.btequ		1,trd1ic	; 
ilvl2_trd1ic	.btequ		2,trd1ic	; 
ir_trd1ic		.btequ		3,trd1ic	; Interrupt request bit
;
treic			.equ		004ah		; Timer RE interrupt control register
ilvl0_treic		.btequ		0,treic		; Interrupt priority level select bit
ilvl1_treic		.btequ		1,treic		; 
ilvl2_treic		.btequ		2,treic		; 
ir_treic		.btequ		3,treic		; Interrupt request bit
;
s2tic			.equ		004bh		; UART2 transmit interrupt control register
ilvl0_s2tic		.btequ		0,s2tic		; Interrupt priority level select bit
ilvl1_s2tic		.btequ		1,s2tic		; 
ilvl2_s2tic		.btequ		2,s2tic		; 
ir_s2tic		.btequ		3,s2tic		; Interrupt request bit
;
s2ric			.equ		004ch		; UART2 receive interrupt control register
ilvl0_s2ric		.btequ		0,s2ric		; Interrupt priority level select bit
ilvl1_s2ric		.btequ		1,s2ric		; 
ilvl2_s2ric		.btequ		2,s2ric		; 
ir_s2ric		.btequ		3,s2ric		; Interrupt request bit
;
kupic			.equ		004dh		; Key input interrupt control register
ilvl0_kupic		.btequ		0,kupic		; Interrupt priority level select bit
ilvl1_kupic		.btequ		1,kupic		; 
ilvl2_kupic		.btequ		2,kupic		; 
ir_kupic		.btequ		3,kupic		; Interrupt request bit
;
ssuic			.equ		004fh		; SSU interrupt control register
ilvl0_ssuic		.btequ		0,ssuic		; Interrupt priority level select bit
ilvl1_ssuic		.btequ		1,ssuic		; 
ilvl2_ssuic		.btequ		2,ssuic		; 
ir_ssuic		.btequ		3,ssuic		; Interrupt request bit
;
iicic			.equ		004fh		; IIC interrupt control register
ilvl0_iicic		.btequ		0,iicic		; Interrupt priority level select bit
ilvl1_iicic		.btequ		1,iicic		; 
ilvl2_iicic		.btequ		2,iicic		; 
ir_iicic		.btequ		3,iicic		; Interrupt request bit
;
cmp1ic			.equ		0050h		; Compare 1 interrupt control register
ilvl0_cmp1ic	.btequ		0,cmp1ic	; Interrupt priority level select bit
ilvl1_cmp1ic	.btequ		1,cmp1ic	; 
ilvl2_cmp1ic	.btequ		2,cmp1ic	; 
ir_cmp1ic		.btequ		3,cmp1ic	; Interrupt request bit
;
s0tic			.equ		0051h		; UART0 transmit interrupt control register
ilvl0_s0tic		.btequ		0,s0tic		; Interrupt priority level select bit
ilvl1_s0tic		.btequ		1,s0tic		; 
ilvl2_s0tic		.btequ		2,s0tic		; 
ir_s0tic		.btequ		3,s0tic		; Interrupt request bit
;
s0ric			.equ		0052h		; UART0 receive interrupt control register
ilvl0_s0ric		.btequ		0,s0ric		; Interrupt priority level select bit
ilvl1_s0ric		.btequ		1,s0ric		; 
ilvl2_s0ric		.btequ		2,s0ric		; 
ir_s0ric		.btequ		3,s0ric		; Interrupt request bit
;
s1tic			.equ		0053h		; UART1 transmit interrupt control register
ilvl0_s1tic		.btequ		0,s1tic		; Interrupt priority level select bit
ilvl1_s1tic		.btequ		1,s1tic		; 
ilvl2_s1tic		.btequ		2,s1tic		; 
ir_s1tic		.btequ		3,s1tic		; Interrupt request bit
;
s1ric			.equ		0054h		; UART1 receive interrupt control register
ilvl0_s1ric		.btequ		0,s1ric		; Interrupt priority level select bit
ilvl1_s1ric		.btequ		1,s1ric		; 
ilvl2_s1ric		.btequ		2,s1ric		; 
ir_s1ric		.btequ		3,s1ric		; Interrupt request bit
;
int2ic			.equ		0055h		; INT2 interrupt control register
ilvl0_int2ic	.btequ		0,int2ic	; Interrupt priority level select bit
ilvl1_int2ic	.btequ		1,int2ic	; 
ilvl2_int2ic	.btequ		2,int2ic	; 
ir_int2ic		.btequ		3,int2ic	; Interrupt request bit
pol_int2ic		.btequ		4,int2ic	; Polarity select bit
;
traic			.equ		0056h		; Timer RA interrupt control register
ilvl0_traic		.btequ		0,traic		; Interrupt priority level select bit
ilvl1_traic		.btequ		1,traic		; 
ilvl2_traic		.btequ		2,traic		; 
ir_traic		.btequ		3,traic		; Interrupt request bit
;
trbic			.equ		0058h		; Timer RB interrupt control register
ilvl0_trbic		.btequ		0,trbic		; Interrupt priority level select bit
ilvl1_trbic		.btequ		1,trbic		; 
ilvl2_trbic		.btequ		2,trbic		; 
ir_trbic		.btequ		3,trbic		; Interrupt request bit
;
int1ic			.equ		0059h		; INT1 interrupt control register
ilvl0_int1ic	.btequ		0,int1ic	; Interrupt priority level select bit
ilvl1_int1ic	.btequ		1,int1ic	; 
ilvl2_int1ic	.btequ		2,int1ic	; 
ir_int1ic		.btequ		3,int1ic	; Interrupt request bit
pol_int1ic		.btequ		4,int1ic	; Polarity select bit
;
int3ic			.equ		005ah		; INT3 interrupt control register
ilvl0_int3ic	.btequ		0,int3ic	; Interrupt priority level select bit
ilvl1_int3ic	.btequ		1,int3ic	; 
ilvl2_int3ic	.btequ		2,int3ic	; 
ir_int3ic		.btequ		3,int3ic	; Interrupt request bit
pol_int3ic		.btequ		4,int3ic	; Polarity select bit
;
trfic			.equ		005bh		; Timer RF interrupt control register
ilvl0_trfic		.btequ		0,trfic		; Interrupt priority level select bit
ilvl1_trfic		.btequ		1,trfic		; 
ilvl2_trfic		.btequ		2,trfic		; 
ir_trfic		.btequ		3,trfic		; Interrupt request bit
;
cmp0ic			.equ		005ch		; Compare 0 interrupt control register
ilvl0_cmp0ic	.btequ		0,cmp0ic	; Interrupt priority level select bit
ilvl1_cmp0ic	.btequ		1,cmp0ic	; 
ilvl2_cmp0ic	.btequ		2,cmp0ic	; 
ir_cmp0ic		.btequ		3,cmp0ic	; Interrupt request bit
;
int0ic			.equ		005dh		; INT0 interrupt control register
ilvl0_int0ic	.btequ		0,int0ic	; Interrupt priority level select bit
ilvl1_int0ic	.btequ		1,int0ic	; 
ilvl2_int0ic	.btequ		2,int0ic	; 
ir_int0ic		.btequ		3,int0ic	; Interrupt request bit
pol_int0ic		.btequ		4,int0ic	; Polarity select bit
;
adic			.equ		005eh		; A-D interrupt control register
ilvl0_adic		.btequ		0,adic		; Interrupt priority level select bit
ilvl1_adic		.btequ		1,adic		; 
ilvl2_adic		.btequ		2,adic		; 
ir_adic			.btequ		3,adic		; Interrupt request bit
;
capic			.equ		005fh		; Capture interrupt control register
ilvl0_capic		.btequ		0,capic		; Interrupt priority level select bit
ilvl1_capic		.btequ		1,capic		; 
ilvl2_capic		.btequ		2,capic		; 
ir_capic		.btequ		3,capic		; Interrupt request bit
;
;-------------------------------------------------------
;   UARTi transmit/receive mode register
;-------------------------------------------------------
u0mr			.equ		00a0h
smd0_u0mr		.btequ		0,u0mr		; Serial I/O mode select bit
smd1_u0mr		.btequ		1,u0mr		; Serial I/O mode select bit
smd2_u0mr		.btequ		2,u0mr		; Serial I/O mode select bit
ckdir_u0mr		.btequ		3,u0mr		; Internal/external clock select bit
stps_u0mr		.btequ		4,u0mr		; Stop bit length select bit
pry_u0mr		.btequ		5,u0mr		; Odd/even parity select bit
prye_u0mr		.btequ		6,u0mr		; Parity enable bit
;
u1mr			.equ		00a8h
smd0_u1mr		.btequ		0,u1mr		; Serial I/O mode select bit
smd1_u1mr		.btequ		1,u1mr		; Serial I/O mode select bit
smd2_u1mr		.btequ		2,u1mr		; Serial I/O mode select bit
ckdir_u1mr		.btequ		3,u1mr		; Internal/external clock select bit
stps_u1mr		.btequ		4,u1mr		; Stop bit length select bit
pry_u1mr		.btequ		5,u1mr		; Odd/even parity select bit
prye_u1mr		.btequ		6,u1mr		; Parity enable bit
;
u2mr			.equ		0160h
smd0_u2mr		.btequ		0,u2mr		; Serial I/O mode select bit
smd1_u2mr		.btequ		1,u2mr		; Serial I/O mode select bit
smd2_u2mr		.btequ		2,u2mr		; Serial I/O mode select bit
ckdir_u2mr		.btequ		3,u2mr		; Internal/external clock select bit
stps_u2mr		.btequ		4,u2mr		; Stop bit length select bit
pry_u2mr		.btequ		5,u2mr		; Odd/even parity select bit
prye_u2mr		.btequ		6,u2mr		; Parity enable bit
;
;-------------------------------------------------------
;   UARTi transmit/receive control register0
;-------------------------------------------------------
u0c0			.equ		00a4h
clk0_u0c0		.btequ		0,u0c0		; BRG count source select bit
clk1_u0c0		.btequ		1,u0c0		; BRG count source select bit
txept_u0c0		.btequ		3,u0c0		; Transmit register empty flag
nch_u0c0		.btequ		5,u0c0		; Data output select bit
ckpol_u0c0		.btequ		6,u0c0		; CLK polarity select bit
uform_u0c0		.btequ		7,u0c0		; Transfer format select bit
;
u1c0			.equ		00ach
clk0_u1c0		.btequ		0,u1c0		; BRG count source select bit
clk1_u1c0		.btequ		1,u1c0		; BRG count source select bit
txept_u1c0		.btequ		3,u1c0		; Transmit register empty flag
nch_u1c0		.btequ		5,u1c0		; Data output select bit
ckpol_u1c0		.btequ		6,u1c0		; CLK polarity select bit
uform_u1c0		.btequ		7,u1c0		; Transfer format select bit
;
u2c0			.equ		0164h
clk0_u2c0		.btequ		0,u2c0		; BRG count source select bit
clk1_u2c0		.btequ		1,u2c0		; BRG count source select bit
txept_u2c0		.btequ		3,u2c0		; Transmit register empty flag
nch_u2c0		.btequ		5,u2c0		; Data output select bit
ckpol_u2c0		.btequ		6,u2c0		; CLK polarity select bit
uform_u2c0		.btequ		7,u2c0		; Transfer format select bit
;
;-------------------------------------------------------
;   UARTi transmit/receive control register1
;-------------------------------------------------------
u0c1			.equ		00a5h
te_u0c1			.btequ		0,u0c1		; Transmit enable bit
ti_u0c1			.btequ		1,u0c1		; Transmit buffer empty flag
re_u0c1			.btequ		2,u0c1		; Receive enable bit
ri_u0c1			.btequ		3,u0c1		; Receive complete flag
u0irs_u0c1		.btequ		4,u0c1		; UART0 transmit interrupt cause select bit
u0rrm_u0c1		.btequ		5,u0c1		; UART0 continuous receive mode enable bit
;
u1c1			.equ		00adh
te_u1c1			.btequ		0,u1c1		; Transmit enable bit
ti_u1c1			.btequ		1,u1c1		; Transmit buffer empty flag
re_u1c1			.btequ		2,u1c1		; Receive enable bit
ri_u1c1			.btequ		3,u1c1		; Receive complete flag
u1irs_u1c1		.btequ		4,u1c1		; UART1 transmit interrupt cause select bit
u1rrm_u1c1		.btequ		5,u1c1		; UART1 continuous receive mode enable bit
;
u2c1			.equ		0165h
te_u2c1			.btequ		0,u2c1		; Transmit enable bit
ti_u2c1			.btequ		1,u2c1		; Transmit buffer empty flag
re_u2c1			.btequ		2,u2c1		; Receive enable bit
ri_u2c1			.btequ		3,u2c1		; Receive complete flag
u2irs_u2c1		.btequ		4,u2c1		; UART2 transmit interrupt cause select bit
u2rrm_u2c1		.btequ		5,u2c1		; UART2 continuous receive mode enable bit
;
;-------------------------------------------------------
;   UARTi receive buffer register
;-------------------------------------------------------
u0rb			.equ		00a6h		; UART0 receive buffer register
u0rbl			.equ		u0rb        ;       Low
u0rbh			.equ		u0rb+1		;       High
oer_u0rb		.btequ		4,u0rbh		; Overrun error flag
fer_u0rb		.btequ		5,u0rbh		; Framing error flag
per_u0rb		.btequ		6,u0rbh		; Parity error flag
sum_u0rb		.btequ		7,u0rbh		; Error sum flag
;
u1rb			.equ		00aeh		; UART1 receive buffer register
u1rbl			.equ		u1rb        ;       Low
u1rbh			.equ		u1rb+1		;       High
oer_u1rb		.btequ		4,u1rbh		; Overrun error flag
fer_u1rb		.btequ		5,u1rbh		; Framing error flag
per_u1rb		.btequ		6,u1rbh		; Parity error flag
sum_u1rb		.btequ		7,u1rbh		; Error sum flag
;
u2rb			.equ		0166h		; UART2 receive buffer register
u2rbl			.equ		u2rb        ;       Low
u2rbh			.equ		u2rb+1		;       High
oer_u2rb		.btequ		4,u2rbh		; Overrun error flag
fer_u2rb		.btequ		5,u2rbh		; Framing error flag
per_u2rb		.btequ		6,u2rbh		; Parity error flag
sum_u2rb		.btequ		7,u2rbh		; Error sum flag
;
;-------------------------------------------------------
;   Address match interrupt registers
;-------------------------------------------------------
rmad0			.equ		0010h		; Address match interrupt register0
rmad0l			.equ		rmad0		;       Low
rmad0m			.equ		rmad0+1		;       Middle
rmad0h			.equ		rmad0+2		;       High
;
rmad1			.equ		0014h		; Address match interrupt register1
rmad1l			.equ		rmad1		;       Low
rmad1m			.equ		rmad1+1		;       Middle
rmad1h			.equ		rmad1+2		;       High
;
;-------------------------------------------------------
;   UART
;-------------------------------------------------------
u0tb			.equ		00a2h		; UART0 transmit buffer register ; Use "MOV" instruction when writing to this register.
u0tbl			.equ		u0tb		;       Low
u0tbh			.equ		u0tb+1		;       High
;
u1tb			.equ		00aah		; UART1 transmit buffer register ; Use "MOV" instruction when writing to this register.
u1tbl			.equ		u1tb		;       Low
u1tbh			.equ		u1tb+1		;       High
;
u2tb			.equ		0162h		; UART2 transmit buffer register ; Use "MOV" instruction when writing to this register.
u2tbl			.equ		u2tb		;       Low
u2tbh			.equ		u2tb+1		;       High
;
;-------------------------------------------------------
;   A-D register
;-------------------------------------------------------
ad0				.equ		02c0h		; A-D register 0 
ad0l			.equ		ad0			;       Low
ad0h			.equ		ad0+1		;       High
;
ad1				.equ		02c2h		; A-D register 1
ad1l			.equ		ad1			;       Low
ad1h			.equ		ad1+1		;       High
;
ad2				.equ		02c4h		; A-D register 2
ad2l			.equ		ad2			;       Low
ad2h			.equ		ad2+1		;       High
;
ad3				.equ		02c6h		; A-D register 3
ad3l			.equ		ad3			;       Low
ad3h			.equ		ad3+1		;       High
